In the design of a clock-distribution network, or “clock tree,” for an integrated circuit (IC) such as application specific integrated circuit (ASIC) or a Programmable Logic Device (PLD) some of the major considerations are skew, jitter, delay, duty cycle distortion and power consumption. Various clock tree geometries such as the balanced tree (e.g., the H clock tree) and grid have been used. The H clock tree, in some cases, can provide low clock skew.
In addition to clock tree geometry, a clock tree may be differential, i.e., provide a differential clock signal using differential circuits, or may be single-ended, i.e., a single clock signal using the conventional Complementary Metal Oxide Semiconductor (CMOS) circuits. A single-ended clock tree is typically noisy and prone to duty cycle distortion at high frequencies, but has only dynamic power consumption. On the other hand, while a differential clock tree has good noise immunity and low duty cycle distortion, it consumes static power due to a common mode.
Traditionally, a PLD has used a single ended clock tree. A PLD, for example, a Field Programmable Gate Array (FPGA) such as the Virtex™-II from Xilinx Inc. of San Jose, Calif., receives a single ended clock or differential signal via the ring of IOBs on the perimeter of the FPGA and transfers this clock signal to configurable logic blocks (CLBs) via the single ended clock tree.
As clock speeds for ICs increase, the need for a low noise clock such as a differential clock increased; however, the single ended clock still has advantages, such as lower static power consumption.
Heretofore, there were two principal ways of distributing a clock signal in a PLD, namely, “local” clock-distribution networks and “global” clock-distribution networks. A global clock-distribution network or global clock resource is classically a centralized clock-distribution network. A clock signal driven on a global clock resource may be capable of reaching any clocking point of a PLD. An H clock tree is conventionally used to provide a global clock resource. However, due to the wide span of a global clock-distribution network, they are relatively expensive in terms of semiconductor die area and metallization usage. Furthermore, the total number of global clock resources from generation to generation of PLD conventionally does not change, and thus there is limited latitude in configuring a PLD for clock intensive applications, such as source synchronous applications where a forwarded clock signal is sent or received.
In contrast to global clock-distribution networks, local clock-distribution networks are not formed as dedicated clock resources, but rather are instantiated by configuring programmable interconnect resources of a PLD. In the past, local clock-distribution networks were used for localized clock distribution as well as providing a signal externally to the PLD. Examples of prior applications of local clock-distribution networks include without limitation providing a source synchronous clock signal for a synchronous interface and receiving a forwarded clock signal for a synchronous interface. However, a local clock-distribution network is generally less predictable with respect to timing characteristics, including without limitation skew, of a propagated signal thereon than a global clock-distribution network. This difficulty in predictability makes using a local clock-distribution network for timing intensive applications, such as telecommunications, networking and memory applications with synchronous interfaces, more problematic.
Accordingly, it would be desirable and useful to provide a clock-distribution network that has improved timing predictability over that of a local clock-distribution network, but is not as costly as a global clock-distribution network.